As one of techniques for reducing power consumption, using a potential level state of a chip select signal /CS (in which a symbol/before a signal name CS indicates active low), control is performed so that when a potential level of a signal CSB (which is an inverted signal of the signal CS) is HIGH,                two-phase internal clocks to be supplied to a command, address, and data input system are stopped,        a synchronous type input buffer is stopped, or        a latch circuit portion of an asynchronous type buffer, which uses a flip-flop circuit or the like, is stopped (such that an output signal of a latch circuit does not transition).        
In a synchronous DRAM in particular, only when the chip select signal /CS is LOW, a command or an address is supplied, as described before. When the chip select signal /CS is HIGH, a command or an address is not necessary. Further, when an effective command enters (in a cycle while the chip select signal /CS is LOW), entry of a next command is not performed (usually for several clocks) until when the command is completed. Accordingly, since entry of an effective command is performed at most once in several cycles, operating the circuit that receives unnecessary commands and address signals (of approximately 20 inputs) in each cycle leads to an increase in the power consumption that becomes more unwanted in a higher-speed operation of the synchronous DRAM. An approach to causing the circuit that receives a command or an address to operate only when the chip select signal /CS is LOW, so as to cut back such unnecessary power consumption, is known. As an example where an approach to operating the semiconductor device of this type using a frequency-divided clock signal, so as to support the higher-speed operation in particular, is shown, a description in Patent Document 1 or the like is referred to.
FIG. 1 is a diagram showing a configuration described in Patent Document 1, and shows an input portion of the synchronous DRAM (refer to FIG. 8 in Patent Document 1). FIG. 2 shows timing waveforms of signals for explaining an operation of a circuit in FIG. 1. An external clock signal (CLK) is frequency divided so as to secure an internal timing margin. Then, using two-phase internal clock signals (an internal clock signal CLK-0 and an internal clock signal CLK-180 of opposite phases, with the phases separated to each other by 180 degrees), the chip select signal is controlled. Referring to FIG. 1, the clock signal CLK, a power down signal PD, and the chip select signal /CS are supplied to a clock generation circuit 36, a power down circuit 38, and a chip select circuit 40, from external terminals 30, 32, and 34, respectively. Then, an N-bit signal such as a command, an address, or data is supplied to an input circuit 44 from an external terminal 42. The clock generation circuit 36 includes an asynchronous type input buffer 50, a frequency divider 52 that receives the clock signal output from the input buffer 50, and a timing adjusting unit 53 that receives the frequency-divided clock signals of mutually different phases output from the frequency divider 52. The input buffer 50 becomes inactive when a power down control signal supplied from the power down circuit 38 is LOW and becomes active when the power down control signal is HIGH. The timing adjusting unit 53 includes a DLL (Delay Locked Loop) circuit, for example. The two-phase internal clock signals CLK-0 and CLK-180, generated by the clock generation circuit 36 based on the external clock signal CLK when the input buffer 50 is operated are supplied to each of the circuits.
The power down circuit 38 includes synchronous type input buffers 54 and 55, an asynchronous input buffer 56, a power down control unit 59, and an inverter 60. When a power down signal PD supplied to the external terminal 32 is LOW and instructs power down, the asynchronous type input buffer 56 which consumes small power, and to which a HIGH level output of the power down control unit 59 inverted by the inverter 60 is supplied, is made active, and the synchronous type input buffers 54 and 55, which consume large power, are made inactive by the HIGH level output (power down control signal) of the power down control unit 59. When the power down signal PD then goes HIGH and instructs power on, an output of the power down control unit 59 goes LOW by an output of the input buffer 56. Then, the asynchronous type input buffer 56, which consumes small power, is made inactive, and the synchronous type input buffers 54 and 55, which consume large power, are made active. This output of the power down control unit 59 is supplied to each of the circuits as the power down control signal.
The chip select circuit 40 includes an asynchronous type input buffer 62 and input circuit control units 64 and 65. To the input buffer 62 with the chip select signal /CS supplied thereto, the power down control signal from the power down circuit 38 is supplied. At a time of power on, responsive to the chip select signal /CS from the input buffer 62, the input circuit control units 64 and 65 generate input enable signals that instruct enabling at a HIGH level by switching between falling and rising edges of the internal clock signal CLK-0 or CLK-180, and supplies so generated input enable signals to the input circuit 44.
The input circuit 44 is constituted from N pairs of input buffers 45 and 46. To these input buffers 45 and 46, the power down control signal from the power down circuit 38 and the input enable signals from the chip select circuit 40 are supplied. Since the power down control signal is LOW when a normal operation is performed, a state of the chip select signal /CS is checked by the input circuit control units 64 and 65 in each clock cycle. Only when the chip select signal /CS is LOW, either of the input enable signal −0 and the input enable signal −180 instructs enabling (is made active). Then, a signal supplied from the external terminal 42 is sampled by the input buffers 45 and 46 in synchronization with the internal clock signals CLK-0 or CLK-180, respectively. Each of output signals A-0 and A-180 is supplied to a subsequent internal circuit (not shown).
[Patent Document 1]
JP Patent No. 3549751 (FIG. 8)